1. Field of the Invention
The present invention relates to storage systems for data processing and more particularly to such storage systems having redundant circuits.
2. Prior Art
The following United States Patents and Japanese published application exemplify the state of the art with regard to semiconductor memory arrays having redundant circuits.
U.S. Pat. No. 5,235,548, entitled "Memory With Power Supply Intercept in Redundancy Logic", teaches a conventional low power SRAM with redundant rows in each subarray including power supply disconnect logic to disconnect supply voltage line for a bad row in the array.
Although the '548 patent generally related to memory arrays having redundant logic, the key element of the invention of the '548 patent is the logic for disconnecting the supply voltage from the bad row.
Japanese published application 02-035698 teaches a memory array in which a delay circuit between address input and word line is eliminated by inserting a fuse between a word line driving circuit and the word line and disconnecting the fuse in the case of replacing the word line by a spare word line.
The published application is a good example of the fundamental technique of using fused lines to select between primary and redundant word lines.
However, the published application does not teach Applicant's invention as shown and claimed herein.
U.S. Pat. No. 5,107,464, entitled "Semiconductor Memory System", teaches a semiconductor memory system having a redundant column which is used for replacing a defective column wherein redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches in redundant column select mode the data lines connecting to a data input/output drive circuit from the regular data lines to the redundant data lines.
A circuit according to the '464 patent separates the regular data lines from the input/output drive circuit and thus prevents error data from a defective column from being output from the memory array.
Although the '464 patent teaches a means for replacing a defective column with a redundant column, it does not teach the invention shown and claimed herein. U.S. Pat. No. 4,951,253, entitled "Semiconductor Memory System", teaches the same memory system as does U.S. Pat. No. 5,107,464 discussed above. As stated with respect to the '464 patent, the '253 patent does not teach or suggest the invention disclosed and claimed herein.
U.S. Pat. No. 4,905,192, entitled "Semiconductor Memory Cell", teaches a memory cell array including a spare memory cell array having a first address circuit for designating an address in the memory cell array a second address circuit for designating an address in the spare memory cell array. An error detection circuit for predetermined output based on whether the memory spare array has a fault and a select circuit responsive to the output from the error detection circuit for supplying an activation signal to the select line at an earlier time when there is no fault in the memory array cell and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.
The '192 patent is an example of a prior art implementation which creates a problem solved by the invention shown and claimed herein.
U.S. Pat. No. 4,365,319, entitled "Semiconductor Memory Device", teaches a semiconductor device in which a redundancy memory cell array is incorporated with the main memory cell array. The memory cell array is selected by two sets of decoders and drivers. When the redundant memory cell array is selected by a decoder, the decoder disables one of the sets of decoders and drivers directly, and as a result the other set of decoders and drivers are also disabled.
The '319 patent does not teach nor suggest the invention shown and claimed herein.
U.S. Pat. No. 4,723,227, entitled "Redundant Type Memory Circuit With and Improved Clock Generator", teaches a redundant memory circuit having a normal memory cell array, a decoder circuit for operatively accessing the normal array, a redundant array, a decoder circuit for accessing the redundant array, and a programmable timing control circuit for enabling the first decoder in a first delay period when no fault cell exists in the normal array and at a second longer delay period when a faulty cell exists in the normal array.
The '227 patent has many similarities to the '192 patent described above, in that delay is inserted in the selection of an address for the redundant array if a fault exists in the normal array. However, the patent does not teach nor suggest the invention shown and claimed herein.
U.S. Pat. No. 5,276,360, entitled "Redundant Control Circuit Incorporated in Semiconductor Integrated Circuit Device for Producing Control Signal Indicative of Replacement with Redundant Unit", teaches a control circuit which compares a defective address with an external address to determine whether a redundant word line is driven for a read operation instead of a defective word line assigned to the defective address and keeps a redundant control signal on a precharged output signal line and an active high voltage level in the presence of the external address consistent with the defective address. The precharging unit not only charges the output signal line to the active high voltage level before arrival of the external address, but also keeps the output signal line at the active high voltage level even if a current path is undesirable established form the output signal line to a discharge line in the presence of the external address consistent with the defective address, thereby preventing the defective word line from being undesirably accessed.